The present invention relates to a level shift circuit and a semiconductor device. More particularly, the present invention pertains to a level shift circuit for converting a voltage level of an input signal to a predetermined voltage level and outputting the converted signal. The present invention also pertains to a semiconductor device incorporating such a level shift circuit.
Contemporary semiconductor integrated circuit devices have multiple functions. Such devices require a low power supply voltage and multiple power supplies. Thus, an interface circuit of a semiconductor device includes a level shift circuit, such as a charge pump circuit.
FIG. 1 is a schematic circuit diagram of a prior art level shift (charge pump) circuit 100. FIG. 2 is a chart illustrating the waveform of the charge pump circuit 100.
As shown in FIG. 1, the chart pump circuit 100 includes a first inverter 12, a second inverter 11, a pumping capacitor C1, and a p-channel MOS (PMOS) transistor Q1. The charge pump circuit 100 provides its input signal VIN to the capacitor C1 and generates an output signal VOUT, whose voltage is higher than that of the input signal VIN.
The second inverter 11 receives the input signal VIN and is connected to a high potential power supply VD and a low potential power supply (ground) GND. The output terminal of the second inverter 11 is connected to the low potential power supply terminal of the first inverter 12.
The high potential power supply terminal of the first inverter 12 is connected to the high potential power supply VD via the PMOS transistor Q1, which prevents current from flowing in the reverse direction. The capacitor C1 is connected between the high potential and low potential power supply terminals of the first inverter 12. The first inverter 12 receives a voltage VH from the high potential power supply VD and generates an output signal VOUT in correspondence with the value of the high potential voltage VH.
When the voltage of the input signal VIN is equal to the high potential voltage VH, the level of a voltage of the output signal of the second inverter 11, or a first inverter voltage V1, is equal to the GND level (0V). Since the first inverter 12 is provided with the high potential power supply VD, the voltage of the output signal VOUT of the first inverter 12 is equal to the GND level. In this state, the gate of the PMOS transistor Q1 receives the output signal VOUT at the GND level. This activates the PMOS transistor Q1.
The activated PMOS transistor Q1 charges the capacitor C1 by way of the high potential power supply VD. Thus, a voltage V2 at node ND1 between the PMOS transistor Q1 and the capacitor C1 increases to the level of the high potential voltage VH.
With reference to FIG. 2, the voltage of the input signal VIN shifts to the GND level at time t0. This shifts the first inverter voltage V1 from the GND level to the high potential voltage VH level. The first inverter voltage V1 then increases the charge voltage of the capacitor C1 to a level corresponding to the high potential voltage VH. Thus, the node voltage V2 becomes two times greater than the high potential voltage VH (i.e., 2VH). The first inverter 12 functions in correspondence with the voltage V1 (VH) provided to its low potential power supply terminal and the voltage V2 (2VH) provided to its high potential power supply terminal.
Thus, the first inverter 12 receives the high potential voltage VH and generates the output signal VOUT having voltage V2 (2VH) at time t1 (FIG. 2). In this state, the output signal VOUT having voltage V2 (2×VH) is provided to the gate of the PMOS transistor Q1. This deactivates the PMOS transistor Q1.
When the voltage of the input signal VIN shifts from the high potential voltage VH to the GND voltage and the first voltage V1 increases to the level of the high potential voltage VH, the capacitor C1 increases the node voltage V2. Referring to FIG. 2, when the node voltage V2 increases, the shifting of the output signal VOUT is delayed by a time required for the first inverter 12 to function.
In other words, when the node voltage V2 shifts to the 2VH level, the PMOS transistor Q1 is still activated. Thus, charge leaks from the capacitor C1 toward the high potential power supply VD via the transistor Q1. This decreases the rising speed of the node voltage V2. As a result, the voltage shifting speed (i.e., the speed of response to the input signal VIN) of the output signal VOUT decreases.
In the aforementioned prior art device, the capacitor C1 has a large capacitance to counteract the decrease in the response speed. The large capacitance of the capacitor C1 has a sufficient margin with regard to the leak of charge from the capacitor C1 to the high potential power supply VD. Thus, the leak of charge from the capacitor C1 to the high potential power supply VD is largely inconsequential. However, when incorporating the charge pump circuit 100 in a semiconductor integrated circuit, it is difficult to arrange a large capacitor C1 on a semiconductor chip.
Another prior art level shift circuit 200 will now be described. FIG. 3 is a circuit diagram of the level shift circuit 200. As shown in FIG. 3, the level shift circuit 200 includes an input circuit 51 and a shift circuit 52.
The level shift circuit 200 is connected to a first power supply VD1, a second power supply GND, and a third power supply VD3. The level shift circuit 200 receives an input signal IN having the voltage of the third power supply VD3 (third voltage VL) and generates an output signal OUT having the voltage of the first power supply VD1 (first voltage VH). The third voltage VL is set at 1.0V, and the first voltage VH is set at 3.0V.
The input circuit 51 is connected between the third power supply VD3 and the second power supply GND (ground GND). Further, the input circuit 51 includes an n-channel MOS (NMOS) transistor Q34 and a PMOS transistor Q35.
The input circuit 51 inverts the input signal IN to generate an inverted input signal /IN and provides the inverted input signal /IN to the shift circuit 52. The shift circuit 52 receives the input signal IN and the inverted input signal /IN and generates the output signal OUT based on the two signals IN, /IN.
The shift circuit 52 includes a first NMOS transistor Q36, a second NMOS transistor Q37, a first PMOS transistor Q38, and a second PMOS transistor Q39.
The gate of the first NMOS transistor Q36 receives the inverted input signal /IN, and the gate of the second NMOS transistor Q37 receives the input signal IN. In other words, the gates of the first and second NMOS transistors Q36, Q37 receive two complementary signals. The sources of the first and second NMOS transistors Q36, Q37 are connected to the ground GND, and the drains of the NMOS transistors Q36, Q37 are respectively connected to the drains of the PMOS transistors Q38, Q39.
The gate of the first PMOS transistor Q38 is connected to the drain of the second PMOS transistor Q39, and the gate of the second PMOS transistor Q39 is connected to the drain of the first PMOS transistor Q38. The sources of the PMOS transistors Q38, Q39 are connected to the first power supply VD1.
When the level shift circuit 200 receives the input signal IN at the third voltage VL (1.0V), the first NMOS transistor Q36 is deactivated and the second NMOS transistor Q37 is activated. In this state, the first PMOS transistor Q38 is activated, and the second PMOS transistor Q39 is deactivated. Accordingly, the shift circuit 52 generates the output signal OUT at the first voltage VH (3.0V).
When the level shift circuit 200 receives the input signal IN at the GND level (0V), the level shift circuit 200 activates the first NMOS transistor Q36 and deactivates the second NMOS transistor Q37. In this state, the second PMOS transistor Q39 is activated, and the first PMOS transistor Q38 is deactivated. Accordingly, the shift circuit 52 generates the output signal OUT at the GND level (0V).
The first and second NMOS transistors Q36, Q37 are activated and deactivated by the input signal IN at a low voltage. That is, the threshold voltage for activating and deactivating the first and second NMOS transistors Q36, Q37 is low. Accordingly, transistors having a low withstand voltage are used as the transistors Q36, Q37.
FIG. 4 is a graph showing the relationship between the gate-source voltage VGS and the drain current ID in two transistors having different withstand voltages. In FIG. 4, curve A illustrates the characteristic of a transistor having a low withstand voltage (hence, a low withstand voltage device), and curve B illustrates the characteristic of a transistor having a high withstand voltage (hence, a high withstand voltage device).
As apparent from curves A and B in FIG. 4, the threshold voltage for activating the low withstand voltage device is about one half the threshold voltage for deactivating the high withstand voltage device. Accordingly, the first and second NMOS transistors Q36, Q37 are activated and deactivated at a lower gate-source voltage in comparison with a high withstand voltage device.
However, the drain of the first NMOS transistor Q36 receives the first voltage VH (3.0V) via the activated PMOS transistor Q38. In this state, the source-drain voltage of the first NMOS transistor Q36 may exceed its threshold voltage. This decreases the reliability of the first NMOS transistor Q36. The same problem also occurs with the second NMOS transistor Q37.